Roadmap

What's done, what's in progress, and where we're headed.

Done
In Progress
Planned
Dec 2024 Done

TI MSPM0 - First Enablement

  • Zephyr SoC and board support for TI MSPM0G series
  • GPIO, UART, clock control, pin controller - initial drivers
  • Linumiz engineer appointed upstream Zephyr maintainer for MSPM0
  • Downstream development begins, upstream submission pipeline established
Apr 2025 Done

TI MSPM0 - Driver Expansion

  • SPI, ADC, DAC, PWM, DMA, RTC, watchdog, comparator, TRNG, AES
  • MSPM0L series support added alongside MSPM0G
  • CAN-FD driver for automotive body applications
  • Multiple drivers merged into mainline Zephyr
Sep 2025 Done

Infineon AURIX - Architecture Port

  • TriCore architecture port begins - new CPU architecture in Zephyr
  • Kernel bring-up on TC375 Lite Kit evaluation board
  • Toolchain integration and build infrastructure
  • GPIO, UART - first peripheral smoke tests on AURIX
Oct 2025 Done

Infineon Traveo T2G - Initial Enablement

  • Zephyr SoC support for CYT4DN (Arm Cortex-M7 + M0+)
  • Multi-level interrupt controller, clock controller, multi-core boot
  • Board support for KIT_T2G_C2D6M_LITE
  • First downstream customer release
Jan 2026 Done

AURIX - Full Architecture & Peripheral Drivers

  • Scheduler, interrupts, context switch - full TriCore arch support
  • 4 board targets: TC375, TC377, TC397, TC4D7
  • MPU support - user/supervisor isolation, 10/10 corner cases
  • I2C master driver - standard (100k) to high-speed (3.4M)
  • Watchdog, clock control, pin controller, system timer, trap handling
Mar 2026 Done

SPI / QSPI Driver

  • SPI master - 8-bit and 16-bit, all 4 SPI modes
  • Per-CS baud rate and timing configuration
  • PMIC register read/write - production peripheral validated
  • Supports both AURIX QSPI and Traveo T2G SPI controllers
Apr 2026 Done

Upstream Submissions

  • AURIX: mainline Zephyr PR opened - 12,851 lines, 231 files
  • AURIX: 98.76% CI pass rate - 8,886 / 8,998 test cases on hardware
  • MSPM0: multiple drivers accepted into mainline Zephyr
  • Toolchains integrated into Zephyr CI Docker image
May 2026 Done

CAN / CAN FD Driver + Traveo T2G Upstream

  • CAN controller driver - Classic CAN 125 kbps to 1 Mbps, CAN FD up to 5 Mbps
  • Ping-pong stress test - 14,600+ loops, zero errors
  • Traveo T2G: 13 upstream PRs submitted - ADC, CAN, DMA, Flash, I2C, I2S, PWM, SPI, WDT
  • Traveo T2G: CYT4BFC (Body-High) family added alongside CYT4DN
May 2026 Done

Labwire Platform

  • Remote lab - acquire, flash, console from anywhere
  • CI/CD pipeline - automated build, flash, verify on real hardware
  • Open-source debug toolchain (OpenOCD)
  • Peripheral monitor - live CAN, GPIO, I2C visualization
Jun 2026 In Progress

Public Launch & Continued Expansion

  • Traveo T2G upstream review in progress
  • NuttX RTOS port for AURIX TriCore (targeting Asian automotive market)
Jul - Aug 2026 Planned

LIN + UART Async

  • LIN master/slave driver
  • UART async API with DMA support
  • Body electronics enablement - windows, mirrors, seats, climate
Oct 2026 Planned

Zephyr 4.5 - Upstream Merge

  • Architecture port merged into mainline Zephyr
  • Core arch + basic drivers upstream (foundation)
  • CI green with toolchain in Zephyr Docker image
  • Flash (NVM) driver - FOTA, calibration storage, bootloader
Nov - Dec 2026 Planned

ADC Driver

  • ADC driver - temperature, pressure, voltage, current sensing
  • Multi-channel scanning, result FIFO
  • Core of powertrain and chassis ECUs
Jan - Feb 2027 Planned

DMA + Mailbox

  • DMA driver - high-throughput data movement
  • CAN gateway, ADC sampling, Ethernet DMA channels
  • Inter-core mailbox (IPC) for multi-core communication
Apr 2027 Planned

Zephyr 4.6 LTS4 - Customer Delivery

  • Long-term support release - ~5 years upstream maintenance
  • Customer-specific BSP bring-up on custom PCB
  • J1939 stack integration on top of CAN subsystem
  • Ethernet v1 + MDIO - gateway, DoIP
  • Safety artifacts - IEC 61508 / ISO 26262
  • Ideal baseline for automotive SOP planning
May - Jun 2027 Planned

Timer & PWM

  • Hardware timer module driver
  • PWM output, input capture, dead-time control
  • Motor control (BLDC, stepper), injector timing
Jul - Aug 2027 Planned

Automotive Sensor Buses

  • SENT driver - throttle position, pressure, wheel speed
  • PSI5 driver - airbag accelerometers, safety-critical sensors
  • Point-to-point protocols replacing analog interfaces
Oct 2027 Planned

Zephyr 5.0 + Power & SMP

  • Start of 5.x release cycle
  • Power management - sleep, standby, wake-up modes
  • Multi-core SMP - parallel processing across cores
  • Complete Tier 1 + Tier 2 automotive peripheral coverage
H1 2028 Planned

Next-Gen Protocols

  • CAN XL driver - 2,048-byte payload, 20 Mbit/s
  • FlexRay - legacy safety-critical chassis bus
  • Hardware fault monitoring (ASIL)
  • Counter / timer - wheel speed, crank/cam position
H2 2028 Planned

High-Speed Links & Routing

  • Additional Ethernet + high-speed serial links
  • Hardware CAN / data routing engines
  • SDMMC + expanded SPI - data logging
  • Motor sensor + serial sensor interfaces
H1 2029 Planned

Security & Standby

  • Secure boot, hardware crypto, key storage
  • Standby controller + voltage/temperature monitoring
  • Accelerator interfaces for next-gen silicon
Oct 2029 Planned

Zephyr 5.4 LTS5 - Full Platform

  • Audio (I2S) + high-resolution PWM
  • Platform consolidation and hardening
  • Complete automotive peripheral coverage - 30+ drivers
  • Second long-term support baseline

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